Due to the massive complexity of contemporary embedded applications and integrated systems, long effort has been invested\r\nin high-level synthesis (HLS) and electronic system level (ESL) methodologies to automatically produce correct implementations\r\nfrom high-level, abstract, and executable specifications written in programcode. If the HLS transformations that are applied on the\r\nsource code are formal, then the generated implementation is correct-by-construction. The focus in this work is on applicationspecific\r\ndesign, which can deliver optimal, and customized implementations, as opposed to platform or IP-based design, which\r\nis bound by the limits and constraints of the preexisting architecture. This work surveys and reviews past and current research in\r\nthe area of ESL and HLS. Then, a prototype HLS compiler tool that has been developed by the author is presented, which utilizes\r\ncompiler-generators and logic programming to turn the synthesis into a formal process. The scheduler PARCS and the formal\r\ncompilation of the system are tested with a number of benchmarks and real-world applications. This demonstrates the usability\r\nand applicability of the presented method.
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